Kay Annamalai, director of marketing, Pericom Semiconductor, spoke

Kay Annamalai, director of marketing, Pericom Semiconductor, spoke to Dilin Anandand and Abhishek Mutha of EFY about the importance of clocks, common design challenges and the difficulties faced in mixed-signal design.
 
Could you elaborate on the Internet of Things—growth of smart devices using technology like low-power Bluetooth 4.0—and how selecting the right components will help design engineers?
Today, all objects and humans are interconnected via Internet and other wireless connectivity options. Materials and vehicles are tagged and monitored, buildings are secured through surveillance, and energy storage and transmission are all monitored and controlled through smart meters that are connected to the network. To promote this further, we need small, low-power devices for monitoring and connectivity. Components like low-power, small-size crystal oscillators, tiny load switches and level shifters will all help in designing these small devices. Overall, designers need to focus on reducing power consumption of these systems.
 
What are the latest solutions that help reduce power consumption in a circuit?
The latest power switches offer very low resistance, standby and shutdown current, and also protect against current-overload and short-circuit conditions in a circuit. On the other hand, the latest low dropout regulators (LDOs) make less noise and offer high ripple rejection and low standby current. Also, current microprocessor supervisory circuits offer voltage-monitoring, power-up reset and watchdog functions. A combination of these solutions will enable engineers to build more efficient circuits that would consume much less power. For embedded designs, engineers can utilise microprocessor supervisory circuits, power switches and LDOs.
 
How important are clocks—be it ICs or real-time—for enabling high-speed applications?
Clocks are the heart of every system. Not only do they need to be stable and accurate but they also need to perform in terms of jitter, especially for high-speed applications like 10Gb Ethernet and 12Gb SAS in storage. Moreover, they need to consume little power.
 
What are the latest advances in timing solutions available for design engineers?
The latest timing solutions are noteworthy, as they now include low-jitter, high-frequency and small-sized crystal oscillators, as well as clock generators that integrate multiple frequencies and multiple copies of the frequencies. We also have high-speed signal-conditioning serial connectivity solutions up to 12.5 Gbps for high-speed backplanes, which include low-voltage, low-power, multi-port drivers andvery high-bandwidth signal switch multiplexers for port expansion.
 
What would a next-generation development in this vertical look like?
Next-generation developments include going up to 40 Gbps and 100 Gbps for Ethernet to cater to fast-growing connectivity requirements for Internet. For these data rates, timing solutions that can provide 0.2p RMS jitter are essential for robust system performance.
 
There are different types of crystal oscillators. Could you elaborate on how designers can make use of these in their products?
Oscillators can be broadly classified as kHz oscillators, MHz CMOS oscillators, MHz differential oscillators, VCXOs and TCXOs. These are used to provide a stable source of signal and hence the designers don’t have to worry about matching the crystal to their ASIC or standard ICs. Crystals are used when they are already in a reference design for low frequencies of up to 40 MHz with specific load capacitance and interface known and where jitter is not critical. For emerging high-speed wireless applications with data rates of up to 1 Gbps, it is important to have a precise timing source with the known jitter.
 
Which crystal oscillator can be used for what application?
32kHz oscillators are increasingly being used in portable devices like tablets, ultrabooks and smartphones, and infotainment. A low-power 32kHz crystal oscillator has very low current consumption of only 10 μA and frequency stability of ±20 ppm, whereas commonly available tuning fork-based 32kHz oscillators have frequency stability of -120 to +30 ppm. MHz CMOS oscillators are used with up to 156.25MHz output for applications ranging from wireless access points, residential gateways, 10Gb Ethernet and GPON to video surveillance, tablets, IP set-top boxes and digital video recorders. MHz differential oscillators are used in high-speed networking, storage and telecom applications. Here jitter is very important for applications such as 10Gb Ethernet, 6Gbps or 12Gbps SAS, and 10 GEPON. VCXOs are used to provide precise output frequency based on control input, such as in VDSL receives input reference and base station applications. TCXOs are used to provide precise timing reference for RF applications like those in smartphones.
 
What’s happening in the interface logic section? What kind of advances can we expect in the coming years?
Interface logic includes a broad category of level shifters. A system-on-chip (SOC) runs on very low voltage, while interface connectivity runs on higher voltages. For these, you need universal level shifters from 0.9 V up to 5.5 V. These level shifters find applications in portable devices and in I2C bus repeaters where two different supply voltages are encountered.
 
What are the key features of redriver signal conditioners and how do they help the embedded products that they go into?
Key features of redrivers are support for various power saving modes during receive idle, hard disk drive unplug and standby conditions, power supply voltage down to 1.05 V, high output swing, and I2C programming of redriver configurations such as transmit output swing, de-emphasis and receive equalisation. These help embedded applications that need these power-saving options. Additionally, there is the flexibility of one to four port offerings depending on the number of channels that need redriving.
 
How difficult is it to design mixed-signal ICs? What are the challenges?
Mixed-signal design is very different from VLSI design methodology. First of all, the design engineer needs to understand the logic function and transistor-level characteristics, which means the physics of the microelectronics. The mixed-signal design knowledge is a process of accumulation. Mixed-signal design has several tools in terms of process, geometry, and on-board passive and transistor level components to achieve the required function and performance. In terms of challenges, for PLL, jitter and lock time are important parameters. For redriver, optimizing the eye opening is important. For differential signal switches, minimizing the insertion loss, return loss, crosstalk and off isolation is important.
 
Could you tell us more about conditioning of high-speed signals and its importance today?
Data rates are increasing in both networking and storage, and there is a definite need to drive these internally as well as externally at high speeds and for longer distances. Even at 6Gbps speed for SATA applications, driving from the chipset is not strong beyond 15 cm (6 inches) of PCB trace and hence redrivers are required internally. Currently, redrivers are required for Express, USB, HDMI, DP, SAS/ SATA and 10 GE 
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